frequency divider

A frequency divider takes a frequency and slows it down. How much depends upon how you use the frequency divider. There are many ways to create a frequency divider. You won't use them all, but just remember that each has its own advantages and disdavantages.

There are chips that are made specifically for frequency division, FPGAs can use code to divide frequencies, and there are a handful of other ways using simple logic. The way that will be described here will use a D flip-flop, as that's where a frequency divider was mentioned.

For this example we are going to take a 2MHz clock and divide it down to 1MHz. This is only for illustrating how to do frequency division with a D flip-flop.

             _______
            |       |
          --|D     Q|--
            |      _|
          --|CLK   Q|--
             -------

        /------------------\
        |    _______       |
        |   |       |      | 
        \---|D     Q|---   |
            |       |      |
 2MHz ------|CLK  \Q|------/
             -------

And the output from Q is a 1MHz clock.

Here's how the above circuit works. When power is applied to the chip, the values of Q and \Q will be 0 and 1, respectively. When the clock signal goes high, D takes its value, which is the 1 from \Q, and gives it to Q. Since Q has changed from a 0 to a 1, \Q has to change from a 1 to a 0. Q and \Q are like night and day. They always have to be the opposite of each other.

Q and \Q will won't change again until the beginning of the next clock cycle when CLK goes high again. When that happens, Q becomes 0 and \Q becomes 1. Which puts us right back where we started, only two clock cycle later.

So what just happened? It becomes easier to understand if you focus just on Q. The value of Q only changes when the clock signal goes high. When the clock signal first goes high, Q becomes a 1. One clock cycle later, Q becomes a 0. On the third clock cycle, Q becomes a 1 again. So, Q goes up and down just like the clock cycle, only at a slower pace.

         Timing diagram
---------------------------------
         __    __    __    __
CLK     |  |  |  |  |  |  |  |
      --    --    --    --    --
---------------------------------
      __       _____       _____
D       |_____|     |_____|

---------------------------------
         _____       _____
Q     __|     |_____|     |_____

---------------------------------
      __       _____       _____
\Q      |_____|     |_____|

---------------------------------

Notice how the D, Q, and \Q are more stretched out then CLK?. They are twice as long, in fact. We just slowed the clock cycle in half. If you want to slow the clock cycle in half again, use another D flip-flop, like so

        /------------------\     /-----------------\
        |    _______       |     |   _______       |
        |   |       |      |     \  |       |      |
        \---|D     Q|------+--\   --|D     Q|---   |
            |       |      |  |     |       |      |
 2MHz ------|CLK  \Q|------/  \-----|CLK  \Q|------/  
             -------                 -------

The question came up, "why you would want to slow down the frequency in the first place?" And the best example that we would all recognize is an analog modem. Most analog modems can operate at 56.6k, 36.4k, 28.8k, 14.4k, 9.6k, down to 300bps. Each different speed requires a different frequency. So, instead of putting half a dozen oscillators on a modem, one frequency can be used and divided down to the speed that is needed.

There are other reasons to divide a frequency, e.g. the need for all the different clock frequencies to be synchronous with each other, but these are design dependent requirements.