The first Acorn RISC Machine CPU, known as the ARM1, was designed by the advanced research and development team at Acorn Computers Ltd between 1983 and 1985. It was targetted as a co-processor expansion to the popular BBC Micro, in order to accustom third party developers to the new platform before releasing the next series of machines.
In October 1983, after the success of the BBC choosing their Proton design for their microcomputer venture, Acorn was already working on its next generation of personal computers. The R&D team were given the task of finding a replacement for the venerable 6502 series, which had to be scalable and significantly more powerful than the 8-bit core of the Rockwell processor.
After evaluating many third party processors, including National Semiconductor's 16032 and Motorola's 68000, they came to the conclusion that they needed intellectual control of a processor core if they were to produce their own computers. Intel refused to licence their 80286 core (they were "not interested in selling cores -- only microprocessors", recalled Acorn's Hermann Hauser), and so the development of a custom Rationalised Instruction Set Computer began.
Sophie Wilson drew on her low-level software experience, gained writing much of the original operating system and all of the BBC BASIC interpreter, to design the rationalised instruction set of the ARM. Relative ease of transition from the 6502 was borne in mind, but foremost were the concepts of fixed instruction length, load/store architecture, and
Steve Furber was the lead hardware designer on the ARM project. His design was evaluated and tweaked using a software simulator on a BBC Micro with a second 6502 processor. The physical layout of the ARM was done in conjunction with VLSI Technology, who also partnered with Acorn on designing the VIDC video controller, MEMC memory controller, and IOC input/output controller support chips.
The first fabrication was at 3.5µm, on the 26th of April 1985, at VLSI Technology, and immediately yielded working silicon. Acorn was delighted with its success: in eighteen months and five man years, ARM1 met all the stated design goals, ran at 2MHz, and used fewer than 25,000 transistors. As soon as the ARM1 co-processor kits were produced, work began on improvements for its successor, the ARM2, which would be used in the Acorn Archimedes series of personal computers.
The ARM is a unique architecture, but carries many standard RISC traits. Most importantly, it has a fixed instruction length of 32 bits, and it is a load/store architecture: the only instructions which operate on memory are for loading values into registers, and storing register values in memory. All registers are general-purpose, and the instruction set is orthogonal (instructions are not tied to any particular register; there are no LDA, LDX, LDY opcodes, for example).
Finally, and unique to ARM, all instructions are executed on one of sixteen possible conditions. A four bit field in each instruction is compared with the processor flags to determine whether or not to execute the instruction; the field includes an "always" possibility, and a "never" setting for no-ops. Conditional execution saves many short branches, which helps stop pipeline stalling, without sacrificing processor throughput or code density.
There are sixteen general-purpose registers, labelled R0 to R15. By convention, R13 is used as the stack pointer, and has the alias SP. A BL (branch-and-link) instruction stores the correct return address in R14, also known as the link register or LR. R15 contains the word-aligned 26-bit program counter, two bits of processor mode, and six bits of processor status flags, and is aliased to PC.
The four processor modes are USR (user mode), IRQ (interrupt mode), FIQ (fast interrupt mode), and SVC (supervisor mode). The supervisor and interrupt modes have separate R13 and R14 registers, and in order to service high priority interrupts with minimum latency due to register shuffling, fast interrupt mode has separate R10 through R14 registers.
ARM1 has many different addressing modes, which is unusual for a RISC processor. There are seperate instruction formats for data processing, single register data transfer, multiple register data transfer, branch, and software interrupt instructions. In addition, the third operand in data processing instructions can be either a register or an 8-bit constant, and optionally shifted or rotated. This makes for a very versatile assembly language, which is exeptionally easy to work with (indeed, almost all of RISC OS is written in assembler).
Instructions include register manipulation (move registers, and load and store on 32-bit registers, bytes, and multiple registers), arithmetic (two operand add, subtract, reverse subtract, all with and without carry; left and right arithmetic shift, logical shift, and rotate), comparison and logic (compare, test, test equivalence, and, or, exclusive or, bit clear), branch and branch with link, and the software interrupt. The latter instruction is one of the most important: it allows user mode software to call operating system routines in supervisor mode, passing arguments in registers. Additionally, operating system extensions can provide software interrupts of their own, allowing ease of extensibility.
A three stage fetch-decode-execute pipeline is employed, including a quirky "free" rotate or barrel shift for every instruction. This, along with conditional execution, gave the ARM 1 a high instructions per cycle ratio of around 0.6 on average.
- Only a few hundred ever fabricated
- Used in: co-processor expansion for the BBC Micro
- Clock: 2MHz
- Fabrication: 3.5µm CMOS
- Registers: 16 general purpose, selectively banked
- Pipeline: three-stage
- Cache: none
- Addressing: 26-bit
- Architecture: ARMv1
- Notable features: first commercial RISC processor
"The ARM RISC Chip", Atack/van Someren, Addison-Wesley, 1993
Electronics Weekly, 29 April 1998
"ARM Assembly Language", Ginns, Dabs Press, 1988